1. Field of the Invention
The present invention relates to oscillating circuitry built in integrated circuitry, for generating and furnishing an internal clock to other components disposed within the integrated circuitry and, more particularly, to built-in oscillating circuitry with multiple oscillating modes which can oscillate in solid oscillating mode by means of an external solid oscillator such as a ceramic resonator or a crystal resonator, and oscillate in RC oscillating mode by means of an external RC circuit comprised of a resistor and a capacitor, so as to generate an internal clock signal.
2. Description of the Prior Art
Referring now to FIG. 6, there is illustrated a schematic circuit diagram showing the structure of a prior art oscillator built in integrated circuitry. The prior art oscillator can oscillate in solid oscillating mode. In FIG. 6, reference numeral 1 denotes integrated circuitry, 2 and 3 denote external terminals, 4 denotes an inverter connected between the external terminals 2 and 3, 5 denotes a feedback resistor connected, in parallel with the inverter 4, to the external terminals 2 and 3, 6 denotes an external ceramic resonator connected between the external terminals 2 and 3, and 7 and 8 denote capacitors connected to the external terminals 2 and 3, respectively.
In operation, when a voltage is applied to the oscillator, the ceramic resonator 6 starts to oscillate and a small AC voltage which corresponds to the amount of oscillation is induced across both ends of the ceramic resonator 6. A small change in voltage having a frequency which corresponds to the capacitances of the capacitors 7 and 8 is then applied between the external terminals 2 and 3. As a result, the inverter 4 generates an AC voltage V0 which is synchronized with the small change in voltage applied to the external terminal 2 and the AC voltage is furnished, as the internal clock, to other components disposed within the integrated circuitry 1.
Referring now to FIG. 7, there is illustrated a schematic circuit diagram showing the structure of another prior art oscillator built in integrated circuitry. The prior art oscillator can oscillate in RC oscillating mode. In FIG. 7, reference numeral 1 denotes integrated circuitry, 9 denotes an external terminal, 10 and 11 denote reference voltage generating resistors for generating a reference voltage, 12 denotes an external resistor connected to the external terminal 9, 13 denotes an external capacitor connected to the external terminal 9, 14 denotes a comparator for comparing a voltage at the external terminal 9 with the reference voltage, 15 denotes an N-channel MOS transistor or NMOS which can be turned on or off according to a comparison result from the comparator 14 so as to attract a current from the external terminal 9, 16 denotes a delay circuit disposed between the output of the comparator 14 and the gate of the NMOS 15, and 17 denotes an inverter for inverting the voltage at the external terminal 9 so as to furnish the inverted voltage.
In operation, when a voltage is applied to the oscillator, the voltage at the external terminal 9 starts to increase with a time constant which corresponds to the impedance of the RC circuit comprised of the external resistor 12 and the external capacitor 13. When the voltage at the external terminal 9 exceeds the reference voltage generated by the reference voltage generating resistors 10 and 11, the output level of the comparator 14 is inverted. Furthermore, after a delay defined by the delay circuit 16, the voltage applied to the gate of the NMOS 15 is inverted. A current then starts to flow from the source of the NMOS 15 to the drain of the NMOS 15. As a result, a charge stored on the external capacitor 13 is attracted by the NMOS 15 and hence the voltage at the external terminal 9 is decreased. After that, when the voltage at the external terminal 9 becomes lower than the reference voltage, the output level of the comparator 14 is inverted again, that is, it returns to the original level, and the NMOS 15 is therefore turned off. As a result, the external capacitor 13 starts to become charged. In this manner, the voltage at the external terminal 9 is varied at intervals determined by the delay time defined by the delay circuit 16 and the response speed of the RC circuit comprised of the external resistor 12 and the external capacitor 13. The inverter 17 inverts and furnishes the varying voltage at the external terminal 9 as the internal clock.
It is to be noted from comparison between the two prior art oscillators that while the former solid-type conventional oscillator is comparatively high in cost as compared with the latter conventional CR-type oscillator, the former solid-type oscillator can generate a clock with a higher degree of accuracy.
A problem with such the prior art built-in oscillators which are so constructed as mentioned above is that since providers need to prepare a variety of integrated circuits having the same function the number of which is equal to a variety of built-in oscillators, it is difficult for providers to expect the economies of scale in manufacturing, and users have to select one from the variety of integrated circuits by not only doing a side-by-side function evaluation, but also considering which oscillating mode is suitable for the uses of a desired integrated circuit.
As recent years have seen significant advances in the area of integration of integrated circuitry, oscillating circuitry built in integrated circuitry which can oscillate in either one of solid oscillating mode and RC oscillating mode as disclosed in Japanese Patent Application Laying Open (KOKAI) No. 6-260836 has been proposed in order to overcome the above problem. Referring next to FIG. 8, there is illustrated a schematic circuit diagram showing the structure of the built-in oscillating circuitry. In the figure, reference numeral 26 denotes a first oscillator which can oscillate in either one of solid oscillating mode and RC oscillating mode, 27 denotes a second oscillator, 28 denotes a clock selection circuit for selecting one from a clock from the first oscillator 26 and another clock from the second oscillator 27 so as to furnish the selected clock as an internal clock, 18 and 19 denote external terminals connected to the first oscillator 26, 20 and 21 denote buffers each having a function of controlling its output, 22 denotes an inverter, 23 denotes a capacitor, 24 denotes a switch for changing the connection of the terminal 18 from the buffer 21 to the buffer 20 and the capacitor 23, and vice versa, 25 denotes another switch for changing the connection of the terminal 19 from the buffer 21 to the inverters 22, and vice versa, and 29 and 30 denote external terminals connected to the second oscillator 27.
First, it is assumed that an external resistor is connected to the external terminals 18 and 19 of the first oscillator 26, and the switch 24 is set to connect the terminal 18 with the buffer 20 and the capacitor 23 and the switch 25 is set to connect the terminal 19 with the inverters 22. In this case, when, for example, the output level of the inverter 22 having it output connected to the switch 25 makes a LOW to HIGH transition, a current flows through the capacitor 23 and the external resistor not shown and, after a delay which corresponds to the time constant of the RC circuit, the voltage at the external terminal 18 goes high. As a result, the output of the inverter 22 having it output connected to the switch 25 returns to a low logic level after the expiration of a predetermined time interval.
Next, it is assumed that a feedback resistor and a ceramic resonator are connected between the external terminals 18 and 19 of the first oscillator and two capacitors are connected to the two external terminals 18 and 19, respectively, and the switch 24 is set to connect the terminal 18 with an input of the buffer 21 and the switch 25 is set to connect the terminal 19 with the output of the buffer 21. In this case, the ceramic resonator and the two capacitors not shown generates a change in voltage having a given frequency. In response to the change in voltage applied to the external terminal 18, the buffer 21 generates a clock signal and then the feedback resistor not shown shapes the waveform of the clock signal.
The second oscillator 27 is so constructed as to oscillate and generate a clock in one oscillating mode. After the prior art oscillating circuitry releases from its reset state, the clock selecting switch 28 is controlled so that the clock from the second oscillator 27 is furnished as the internal clock.
As previously mentioned, while the conventional oscillating circuitry built in integrated circuitry as shown in FIG. 8 can oscillate in either one of the two oscillating modes, the oscillating circuitry suffers from a drawback that since the rising and falling timing of edges of the clock from the first oscillator 26 is not coincident with that of edges of the clock from the second oscillator 27, a clock having a frequency greater than those of the clocks from the first and second oscillators 26 and 27 can be generated when switching the selection between the clocks and a so-called spike noise can be generated. If such a high-frequency clock is delivered to the other components of the integrated circuitry, a sufficient data setup time cannot be provided, and hence latching operations are made unstable and malfunctions occur in the other components within the integrated circuitry. Therefore, even if the integrated circuitry equipped with the prior art oscillating circuitry is reset, the restoration of the integrated circuitry cannot be ensured with the integrated circuitry held in its reset state.
In addition, the prior art oscillating circuitry needs the different two pairs of external terminals 18, 19 and 29, 30 for the first and second oscillators 26 and 27. This causes an increase in the number of pins needed by the integrated circuitry.